The present invention relates to a sampling circuit generally used as part of a sample-and-hold circuit so as to sample an analog input signal and generate sampling signals in response to a control signal at a series of definite points in time.
Sample-and-hold circuits are known as analog storage devices which permit readout and/or storage of the value x(t.sub.1) of a variable analog signal x(t) at a specified sampling time t.sub.1, and they have been steadily increasing in importance.
The sample-and-hold circuit generally includes a metal oxide semiconductor (MOS) transistor which serves as an analog switch connected between a buffer amplifier and an operational amplifier. A voltage level of the analog input signal is sampled at a specified sampling time by the switching operation of the MOS transistor in response to an externally supplied control signal. The MOS transistor is rendered nonconductive during a holding interval so as to electrically separate the sampling circuit from the input stage of the operational amplifier. Therefore, the sampled voltage is held by a capacitor connected in parallel with the operational amplifier.
However, in the circuit arrangement described above, the MOS transistor has poor linearity in its current-voltage characteristic curve while it is rendered conductive, and the linearity of the sampling circuit is degraded accordingly. When the frequency of the input signal is increased, a noise component such as distortion or a nonlinear term is superposed on the output signal at the sampling time, thereby degrading the frequency characteristics of the sampling circuit, resulting in a pronounced drawback.